System and method for erase test of integrated circuit device having non-homogeneously sized sectors

ABSTRACT

A system and method for testing a flash memory device having uniform sectors and smaller, “boot” sectors includes determining uniform and boot test limits based on average erase and APDE time periods of the uniform and boot sectors, respectively. In this way, the erase test results for each sector type is compared against test limits that are based only on that sector type, thereby avoiding excessive false rejects.

TECHNICAL FIELD

[0001] The present invention relates generally to testing integratedcircuit devices such as flash memory devices.

BACKGROUND OF THE INVENTION

[0002] Semiconductor devices, including integrated circuit devices suchas boot-type devices, are tested prior to shipment to ensure qualitycontrol. In the case of boot-type devices known as flash memory devices,the testing can include parametric tests, including testing for shortcircuits, open circuits, various leakage tests, and various signaturetests. Also, the testing can include various performance or functionaltests, such as speed tests and erase time tests. Of importance to thepresent invention is testing a device for erase time.

[0003] Specifically, to determine whether a device can be erasedadequately, each sector in the device is programmed, and then the deviceis erased, sector by sector, with the time period required for erasurebeing recorded for each sector. In the event that any leakage isdetected after an erase operation, a test known as Auto Program DisturbErase (APDE) is performed to cure the leakage, and then the APDE timeperiod is also recorded. A test limit is then calculated that isessentially the average (or, e.g., 1.5 times the average) of the erasetime periods and APDE time periods of all the sectors. If the timeperiods required for any sector exceed the test limit, the device isrejected.

[0004] As recognized by the present invention, for test purposes it hasbeen assumed that flash memory devices have equally-sized sectors, thatis, all the sectors to be tested of flash memory devices are assumed tobe of uniform size. Accordingly, a single test limit has been usedagainst which the erase/APDE times of all sectors are compared.

[0005] The present invention understands, however, that flash memorydevices can have some sectors of one uniform size (typically of a largersize) and other sectors (boot sectors) of other, non-uniform sizes(typically of smaller sizes and, hence, colloquially referred to as“baby sectors”). In these devices, the smaller baby sectors should haveshorter erase times than the larger uniform sectors. Nonetheless,current test procedures still use a single test limit against which allsectors are compared. The present invention recognizes that when asingle test limit is used, it is based on times derived from both theuniform sectors and baby sectors and, hence, might be set too low foruniform sectors, thus resulting in a large number of false rejects.Having made the above critical observations, the present inventionprovides the below-solutions to one or more of the observations.

BRIEF SUMMARY OF THE INVENTION

[0006] A method for testing a semiconductor device having at least onefirst sector of a first sector type (e.g., a uniform sector) and atleast one second sector of a second sector type (e.g., a boot sector)includes measuring at least one first time period, such as erase timeand/or APDE time, that is related to erasing the first sector. Themethod also includes establishing a first test limit based at least inpart on the first time period. Further, the method includes measuring atleast one second time period related to erasing the second sector, andestablishing a second test limit based at least in part on the secondtime period. The first and second test limits are used to determinewhether the device passes or fails an erase test.

[0007] In a preferred embodiment, the device includes many first sectorsand many second sectors, and the first test limit is based at least inpart on an average of first time periods associated with respectivefirst sectors. Likewise, the second test limit is based at least in parton an average of second time periods associated with respective secondsectors.

[0008] As indicated above, more than one time period can be used, andpreferably both erase time and APDE time are used. Accordingly, thepreferred method can include measuring at least one third time periodrelated to erasing the first sector and measuring at least one fourthtime period related to erasing the second sector. The first and secondtime periods can be erase time periods and the third and fourth timeperiods can be APDE time periods. Consequently, the first test limitpreferably is based on the first and third time periods (uniform sectoraverage erase time and uniform sector average APDE time), while thesecond test limit is based on the second and fourth time periods (bootsector average erase time and boot sector average APDE time).

[0009] For each sector, the preferred method can also determine whetherthe time period associated with the sector exceeds the test limitassociated with the time period of the sector. If it does, the device isrejected. At least one parameter test can also be executed on thedevice.

[0010] Other features of the present invention are disclosed or apparentin the section entitled “DETAILED DESCRIPTION OF THE INVENTION”.

BRIEF DESCRIPTION OF DRAWINGS

[0011]FIG. 1 is a schematic view of a flash memory device having uniformsectors and non-uniform sectors;

[0012]FIG. 2 is a flow chart of the overall logic of the presentinvention;

[0013]FIG. 3 is a flow chart of the erase test logic; and

[0014]FIG. 4 is a flow chart of the erase test evaluation logic.

DETAILED DESCRIPTION OF THE INVENTION

[0015] Referring initially to FIG. 1, a semiconductor device, morespecifically a bootable device, and still more specifically a flashmemory device, is shown and generally designated 10. As shown, thedevice includes plural sectors. The sectors labeled “sector 5”, “sector6”, and “sector 7” are all uniformly sized, relatively large sectors.This means they all have the same number of memory cells. On the otherhand, the sectors labeled “sector 0”, “sector 1”, “sector 2”, and“sector 3” are non-uniformly sized, compared to the uniformly sizedsectors, are relatively small and, hence, can be referred to as “babysectors”. These sectors are also known as “boot sectors”. The sectors0-3 can be the same size as each other or, as shown, the sectors 1 and 2can have the same size, sector 0 can be larger than sector 1, and sector3 can be larger than sector 0. In any case, the boot sectors aregenerally smaller than the uniform sectors.

[0016]FIG. 2 shows the overall logic by which the present inventionoperates. Commencing at block 12, certain parameter tests can beexecuted on the device 10. These tests include, but are not limited to,tests for open circuits and short circuits, certain electrical leakagetests including in-leakage, and certain device signature tests. Movingto block 14, performance (functional) tests are conducted, including butnot limited to the section erase test described further below. Then, atblock 16 additional parameter tests can be executed ifdesired/necessary.

[0017] The erase test logic is shown in FIG. 3. Commencing at block 18,all cells in all sectors are programmed, so that the cells can besubsequently erased. Moving to block 20, a DO loop is entered for eachsector. At block 22 the programming time period for each sector isrecorded, as is the sector type/size. Programming time period can, ofcourse, be recorded during the process at block 18, and sector size/typecan likewise be recorded. Moving to block 24, the sector is erased andits erase time period recorded.

[0018] Next, at decision diamond 26 it is determined whether the sectorexperienced any electrical leakage during erasure, and if so, an AutoProgram Disturb Erase (APDE) pulse is generated at block 28 to cure theleakage, i.e., APDE is applied until the leakage is below a threshold.The time period to conduct the APDE test is recorded, and a routineknown as “erase verify” is conducted in accordance with flash memorytest principles known in the art to verify that the sector under test iserased.

[0019] From block 28 or decision diamond 26 when the test there isnegative, the logic moves to decision diamond 30 to determine whetherthe last sector has been tested. If not, the next sector is testedstarting at block 22. At the end of the process of FIG. 3, the test isevaluated at state 32 using the logic of FIG. 4.

[0020]FIG. 4 shows the erase test evaluation logic. Commencing at block34, a DO loop is entered for each sector type/size. For instance, eachsector type might be defined by sectors having exactly the same size asother sectors in that type. Or, two sector types uniformly sized memorysectors, and boot sectors regardless of size, might be defined.

[0021] In any case, at block 36 a test limit for the type under test isdefined. The test limit is based on one or more, preferably both of: theaverage erase time period for sectors in the type, and the average APDEtime period for sectors in the type. In a particularly preferredembodiment, the test limit is defined to be 1.5 times the sum of theaverage erase time period plus the average APDE time period.

[0022] After defining the test limit for the sector type under test, thelogic moves to block 38 to enter a DO loop for each sector in the type.Proceeding to decision diamond 40 it is determined whether either one orthe sum of both of the sector's erase time period plus APDE time periodexceed the test limit. Preferably, the sum of the segment's erase timeperiod and APDE time period are compared to the test limit at decisiondiamond 40. If the sum exceeds the limit, “FAIL” is returned at block 42and the device 10 is rejected. Otherwise, the logic moves to decisiondiamond 44 to determine whether the last sector in the type has beentested, and if not, the next sector is tested starting at decisiondiamond 40. If the last segment in the type has been tested the logicmoves from decision diamond 44 to decision diamond 46 to determinewhether the last sector type has been evaluated, and if not the nextsector type is tested starting at block 36. Otherwise, the logic ends atstate 48.

[0023] The above logic can be embodied in a computer or other digitalprocessor that is programmed to execute method acts in accordance withthe logic, and it can be stored on a computer-readable medium such as ahard disk drive, diskette, optical disk, ROM or RAM, and so on.

[0024] While the particular SYSTEM AND METHOD FOR ERASE TEST OFINTEGRATED CIRCUIT DEVICE HAVING NON-HOMOGENEOUSLY SIZED SECTORS asherein shown and described in detail is fully capable of attaining theabove-described objects of the invention, it is to be understood that itis the presently preferred embodiment of the present invention and isthus representative of the subject matter which is broadly contemplatedby the present invention, that the scope of the present invention fullyencompasses other embodiments which may become obvious to those skilledin the art, and that the scope of the present invention is accordinglyto be limited by nothing other than the appended claims, in whichreference to an element in the singular is not intended to mean “one andonly one” unless explicitly so stated, but rather “one or more”. Allstructural and functional equivalents to the elements of theabove-described preferred embodiment that are known to those of ordinaryskill in the art are expressly incorporated herein by reference and areintended to be encompassed by the present claims. Moreover, it is notnecessary for a device or method to address each and every problemsought to be solved by the present invention, for it to be encompassedby the present claims. Furthermore, no element, component, or methodstep in the present disclosure is intended to be dedicated to the publicregardless of whether the element, component, or method step isexplicitly recited in the claims. No claim element herein is to beconstrued under the provisions of 35 U.S.C. §112, sixth paragraph,unless the element is expressly recited using the phrase “means for”.

What is claimed is:
 1. A method for testing a semiconductor devicehaving at least one first sector of a first sector type and at least onesecond sector of a second sector type, comprising: measuring at leastone first time period related to erasing the first sector; establishingat least a first test limit based at least in part on the first timeperiod; measuring at least one second time period related to erasing thesecond sector; establishing at least a second test limit based at leastin part on the second time period; and using the first and second testlimits, determining whether the device passes or fails an erase test. 2.The method of claim 1, wherein the device comprises plural first sectorsand plural second sectors, and the first test limit is based at least inpart on an average of first time periods associated with respectivefirst sectors and the second test limit is based at least in part on anaverage of second time periods associated with respective secondsectors.
 3. The method of claim 1, further comprising measuring at leastone third time period related to erasing the first sector and measuringat least one fourth time period related to erasing the second sector,the first and second time periods being erase time periods and the thirdand fourth time periods being APDE time periods, the first test limitbeing based at least partially on at least one of: the first and thirdtime periods, the second test limit being based at least partially on atleast one of: the second and fourth time periods.
 4. The method of claim3, wherein the first test limit is based at least partially on both ofthe first and third time periods, and the second test limit is based atleast partially on both of the second and fourth time periods.
 5. Themethod of claim 2, further comprising measuring at least third timeperiods related to erasing respective first sectors and measuring atleast fourth time periods related to erasing respective second sectors,the first and second time periods being erase time periods and the thirdand fourth time periods being APDE time periods, the first test limitbeing based at least partially on at least one of: the first and thirdtime periods, the second test limit being based at least partially on atleast one of: the second and fourth time periods.
 6. The method of claim5, wherein the first test limit is based at least partially on both ofthe first and third time periods, and the second test limit is based atleast partially on both of the second and fourth time periods.
 7. Themethod of claim 1, wherein the act of using includes determining, foreach sector, whether the time period associated with the sector exceedsthe test limit associated with the time period of the sector.
 8. Themethod of claim 1, further comprising executing at least one parametertest on the device.
 9. The method of claim 1, wherein the second sectoris a boot sector.
 10. A device for testing a semiconductor device havingat least one first sector of a first sector type and at least one secondsector of a second sector type, comprising: means for measuring at leastone first time period related to erasing the first sector; means forestablishing at least a first test limit based at least in part on thefirst time period; means for measuring at least one second time periodrelated to erasing the second sector; means for establishing at least asecond test limit based at least in part on the second time period; andmeans for determining, using the first and second test limits, whetherthe device passes or fails an erase test.